As the complexity and power of computing systems increases, the amount of memory required for systems has also increased. This has resulted in the drive for semiconductor memory devices of increased storage capacity. At the same time, the desire for more efficient manufacturing and more compact electronic devices has led to the competing interest of shrinking semiconductor memory devices to as small a size as possible. As a result, there is a continuous drive to arrive at semiconductor memory devices which have as high a density (data bits per physical area) as possible.
A common type of semiconductor memory device is the dynamic random access; memory (DRAM). DRAMs typically include a large number (millions or thousands) of memory cells, each of which can store at least one bit of data. The memory cells are usually arranged into an array configuration of rows and columns. Because the primary function of DRAM is to store data, the DRAM array makes up the majority of the area on a DRAM. Thus, any reduction in the size of a memory cell translates into increased memory density.
While density is an important features of a DRAM, another factor, speed, is also important. One reason for the increase in system computing power is the faster speeds at which such systems operate. For this reason, it is also desirable to provide a DRAM that has a fast operating speed, so that data can be provided to a system at a sufficient rate.
DRAMs are a preferred choice for main system memory as they are typically less costly than other memory types and consume relatively low amounts of power. However, because DRAMs are being used more often in battery operated applications, such as laptop computers, further improvements in power consumption are desirable. Lower power DRAMs can contribute to longer battery lifetimes in battery operated systems.
To better understand the factors involved in DRAM design that impact memory device density, speed and power consumption, the architecture of a conventional DRAM memory array will be reviewed. A typical DRAM array includes memory cells arranged in row and columns, with the memory cells of the same row being commonly coupled to a word line and the memory cells of the same column being commonly coupled to a bit line.
The data stored within the memory cells is accessed according to various DRAM operations which include read operations, write operations and refresh operations. Read and write operations usually begin with the application of an external memory address. Commonly, an applied memory address is multiplexed, with a row address being applied first, and a column address being applied subsequently. The application of the row address results in the activation of a word line. Once activated, the word line couples the data stored within its respective row to the bit lines of the array. The coupling of a row of memory cells to bit lines results in differential voltage signals appearing on the bit lines (or bit line pairs). The differential signals are relatively small, and so must be amplified (typically by a sense amplifier). The application of the column address activates column decoder circuits, which connect a given group of bit lines to input/output circuits.
Referring now to FIG. 1, a prior DRAM array is set forth and designated by the general reference character 100. The DRAM array 100 is arranged as an n.times.m array, having n rows coupled to n word lines (WL0-WLn) and m columns coupled to m sets of bit line pairs (BL0, BL0_-BLm, BLm_). A memory cell is formed where a word line intersects a bit line pair. The memory cells are designated as M00-Mnm, where the first digit following the "M" represents the physical row of the memory cell's location and the second digit represents the physical column of the memory cell's location. For example, M00 is the memory cell located at the intersection of WL0 and bit line pair BL0/BL0_.
The word lines of the DRAM array 100 are driven by a word line driver bank 102 coupled to the word lines (WL0-WLn). The word line driver bank 102 is separated into n separate word line driver circuits, shown as DRV0-DRVn. The word line driver bank 102 is responsive to a row address (not shown) in such a manner that only one word line driver circuit (DRV0-DRVn) will drive its corresponding word line high, when the row address is received. For example, word line driver circuit DRV0 will drive word line WL0 high when the row address value of "zero" is received, and word line driver circuit DRVn will drive word line WLn high when the row address value of "n" is received.
The DRAM array 100 further includes a sense amplifier bank 104 coupled to the bit line pairs (BL0, BL0_-BLm, BLm_). The sense amplifier bank 104 is separated into m separate sense amplifier circuits, shown as SA0-SAm. While all of the sense amplifiers 104 will be activated simultaneously, only selected of the sense amplifiers (SA0-SAm) will pass sensed data to the DRAM outputs (not shown). A sense amplifier (SA0-SAm) will be selected according to a column address applied to a column decoder (not shown) in the DRAM.
The typical DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. Once a storage capacitor has been initially charged, over time, the amount of charge will be reduced by way of a leakage current. Thus, it is important for the DRAM to restore the charge on the capacitor before the amount of charge falls below a critical level, due to leakage mechanisms. The critical level of charge for a storage capacitor arises out of the minimum sensitivity of the DRAM sense amplifiers. The storage capacitor must have enough charge to create a sufficient differential voltage on the bit lines for the sense amplifier to reliably sense. The time needed before the charge on the capacitor falls below the critical level is commonly referred to as the maximum "pause" period.
Typically, the restoration of charge within a DRAM memory cell is accomplished with a refresh operation. Thus, a DRAM should perform a refresh operation on every row in the device before that row experiences the maximum "pause" period. The refreshing operation of a DRAM is considered important as such operations consume a relatively large amount of power because all the bit lines in an array must be driven to refresh the memory cells in a row. One way to reduce power consumption in a DRAM, therefore, is to reduce the rate of charge leakage from the storage capacitor. By doing so, the maximum pause period of the DRAM can be increased, allowing refresh operations to occur with less frequency.
Referring once again to FIG. 1, each memory cell (M00-Mnm) of the DRAM array 100 is shown to contain a pass transistor (shown as n-channel MOSFETs Q00-Qnm) and a storage capacitor (shown as C00-Cnm). Within each memory cell (M00-Mnm) the junction of the source of the each storage capacitor (C00-Cnm) and its associated pass transistor (Q00-Qnm) is shown as a storage node (106-112). The potential at the storage node will determine the logic of the data stored within the memory cell. Thus, a memory cell (M00-Mnm) is accessed in a read, write and refresh operation by coupling its storage node (106-112) to its respective bit line (BL0, BL0_-BLm, BLm_.
In a read cycle, the bit line pairs (BL0, BL0_-BLm, BLm_) are initially at a precharge potential. This potential is typically midway between a logic high and logic low. Thus, assuming Vss=0 volts, the bit lines would be precharged to Vcc/2. The read cycle begins with a row address being applied to the DRAM to activate a word line. The pass transistors in a row of memory cells are turned on, coupling their storage nodes to their respective bit lines (BL0, BL0_-BLm, BLm_. In order to ensure that maximum charge is placed on the bit lines, the selected word line driver circuit will drive its word line to a voltage level that is at least one n-channel threshold voltage (Vtn) above the high logic level of the array (Vcc). The speed of a DRAM is thus dependent upon how fast a word line can be driven from a low potential to a high potential.
Referring once again to FIG. 1, each word line is shown to be coupled to the control gate of all the DRAM cells within its particular row. This arrangement results in a relatively large capacitive load on the word line. In order to reduce the speed required to drive the word line between high and low voltages, it is desirable to make the word line have as little resistance as possible. The polysilicon word line resistance may be reduced by forming a self-aligned silicide (salicide) structure on it. Alternatively, a metal layer may run parallel to and over the polysilicon, and be periodically connected to the polysilicon by way of contacts. Such a structure is often referred to as a "strapped" word line.
When the memory cells of a selected row are coupled to their bit lines, a differential voltage will be generated across the bit line pairs (BL0, BL0_-BLm, BLm_. The value of the differential voltage is dependent upon the logic of the data stored in the memory cell. For example, if it is assumed that memory cell M00 stores a logic "1," capacitor C00 will be charged. Thus, when the data from memory cell M00 is read, bit line BL0 will rise to a potential that is a slightly higher than the potential of bit line BL0_ (which is at Vcc/2). Conversely, if it is assumed that memory cell M00 stores a logic "0," capacitor C00 will be discharged, and when memory cell M00 is read, bit line BL0 will fall to a potential that is a slightly less than that of bit line BL0_ (Vcc/2).
Once differential voltages are established on the bit line pairs (BL0, BL0_-BLm, BLm_) the sense amplifier bank 104 is activated. When activated, the sense amplifiers (SA0-SAm) amplify the voltage differential on the bit lines pairs (BL0, BL0_-BLm, BLm_), to generate data signals having a full logic level (either Vcc or Vss, depending upon the logic level stored in the memory cell). For example, in the event memory cell M00 stored a logic 1, sense amplifier SA0 would drive bit line BL0 to Vcc and bit line BL0_ to Vss. In the case of logic 0, bit line BL0 would be driven to Vss while bit line BL0_ is driven to Vcc.
Because the pass transistors coupled to word line WL0 are still turned on when the differential voltage signals are amplified, fill logic levels will be applied to the bit line pair; (BL0, BL0_ to BLm, BLm_) according to the values originally store therein. Following the same example, if memory cell M00 stores a logic "1", with word line WL0 at a voltage of Vcc+Vtn, a full Vcc level will be applied back to the storage node 106, recharging capacitor C00. In the event of a logic 0, storage node 106 will be discharged to Vss. In this manner, all of the memory cells in an row will have their data restored to a full logic level (Vcc or Vss) by a read operation.
Refresh operations occur in the same fashion as a read cycle, except that the selection of a row is usually accomplished by a counter circuit. Further, the amplified bit line data is not provided as output data.
Write operations occur in a similar fashion to read operations. A row address results in the activation of a word line. A column address will couple write circuitry (not shown) to selected bit lines, to allow high or low logic levels (Vcc or Vss) to be written into selected memory cells. In order to ensure maximum charge is placed on the storage capacitor, the activated word line is driven to one Vt above Vcc, as in the read and refresh operations.
Following a read, write, or refresh operation, the DRAM is allowed to go into a precharge state, in which the word lines will be driven to a low voltage, for example Vss. In this state, the storage nodes (106-112) are isolated from the bit lines (BL0, BL0_-BLm, BLm_), as the pass transistors (Q00-Qnm) will be in a non-conducting state. Because the leakage characteristics of the storage capacitors (C00-Cnm) and pass transistor Q00 are not ideal, once the storage nodes (106-112) are isolated from the bit lines (BL0, BL0_-BLm, BLm_) the charge stored on the storage capacitors (C00-Cnm) will leak away, and the voltage will slowly begin to fall.
As mentioned above, a read or refresh operation must be performed on each row in the DRAM before the charge level on the storage node 106 falls below the critical level. Thus, it is important to make the pass transistors (Q00-Qnm) and storage capacitors (C00-Cnm) as ideal (i.e., have as little leakage) as possible.
The critical charge level of DRAM memory cell storage capacitors is dependent upon the capacitance of the storage capacitor: The larger the capacitance, the greater the amount of charge that can be stored on the capacitor. Having more charge on the capacitor results in more charge that can be lost before the total charge on the capacitor falls below the critical level. Thus, it is important to construct storage capacitor having as large a capacitance as possible. While the capacitance of a storage capacitor can be increased by physically increasing the size of the capacitor, a drawback to such an approach is that other array structures may place constraints on how far the storage capacitor may extend, both laterally and vertically. Furthermore, increasing the size of the storage capacitor will result in a larger array size.
To better understand the constraints imposed on conventional DRAM cells, a side cross sectional view of a memory cell is set forth in FIG. 2. The memory cell is designated by the general reference character 200, and shown to include a pass transistor 202 and a storage capacitor 204 formed on a semiconductor substrate 206. The pass transistor 202 couples the storage capacitor 204 to a bit line 208 in order to allow data to be read from, written to, or refreshed within, the memory cell 200.
The storage capacitor 204 includes a storage node 210 and a top plate 212 separated by a capacitor dielectric 214. The storage node 210 is formed from polysilicon and is coupled to the pass transistor 202. The capacitor dielectric 214 may be silicon dioxide or a silicon dioxide-silicon nitride-silicon dioxide (SiO.sub.2 --Si.sub.3 N.sub.4 --SiO.sub.2) combination. The top plate 212 is formed from polysilicon, and all storage cells on the DRAM array may share the same top plate 212. The top plate 212 may be maintained at a "plate" voltage having a potential equivalent to Vcc/2 that serves to reduce the electric field across the capacitor dielectric 214. The capacitance of the storage capacitor 204 is determined by the surface area of the storage node 210, the dielectric constant of the capacitor dielectric 214, and the thickness of the capacitor dielectric 214 (the distance between the top plate 212 and the storage node 210).
The pass transistor 202 is shown to include a source region 216 and a drain region 218 formed within the substrate 206. The substrate 206 is P-type doped silicon and the source region 216 and drain region 218 are N-type doped silicon. The P-N junction created between the substrate 206 and the source and drain regions (216 and 218) generates a parasitic junction capacitance which limits the performance of the pass transistor 202. The pass transistor 202 also includes a control gate 220 placed between the source region 216 and drain region 218, and separated from the substrate 206 by a thin control dielectric 222. The control gate 220 is polysilicon, and the thin control dielectric 222 may be silicon dioxide, or a combination silicon dioxide-nitride layer.
The pass transistor 202 is coupled to the storage capacitor 204 at the drain region 218. The pass transistor 202 is further coupled to a bit line contact 224 via the source region 216. The bit line contact 224 is coupled to the bit line 208. The bit line 208 is a metal, for example Al, or alternatively, a titanium-tungsten combination (TiW). In operation, when the control gate 220 is at a voltage that is one Vtn above that of the source region 216 or drain region 218, a low impedance path is formed between the storage node 210 and the bit line 208. In this manner, data can be read from, written to, or restored at, the storage node 210. However, if the control gate 220 voltage is less than one Vtn above the source region 216 and drain region 218, the pass transistor 202 forms a high impedance path between the storage capacitor 204 and the bit line 208. In this manner, a low voltage on the control gate 220 (such as Vss) results in the isolation of the bit line 208 from storage node 210, and only unwanted leakage mechanisms may interfere with the data integrity.
One type of unwanted leakage mechanism is current that leaks from the drain region 218 to the source region 216 within the pass transistor 202. This current is represented by the character "Ileak" in FIG. 2. The current Ileak can be problematic, due to short channel effects resulting from a very short channel length. This raises a barrier to the limit to which transistor dimensions can be shrunk, which in turn, places a limitation on how small a DRAM array can be. Short channel effects will further effect the reliability of adjusting the threshold voltage of the pass transistor 202. Because the operation of the pass transistor 202 is dependent upon its threshold, it would be desirable to have greater control over the channel region of the pass transistor 202. It is understood that in an array configuration, the control gate 220 runs the full length of the DRAM array in the row direction, forming the word line, such as WL0 set forth in FIG. 1.
As device geometries continue to shrink, it would be desirable to arrive at a DRAM memory cell that has small feature sizes (such as short channel lengths), greater control over the channel region, a high capacitance storage capacitor, low parasitic capacitance, and greater control over the channel region. Such DRAM cell would preferably be implemented in a high-density memory array.